1. Field of Invention
The present invention relates to a method of planarizing inter-metal dielectric (IMD) layers, and more particularly to a method of improving the planarization of an inter-metal dielectric layer using spin on glass (SOG) such that the formation of poisoned vias is prevented.
2. Description of Related Art
To match the ever increasing complexity and precision requirements of semiconductor integrated circuits, two or more metal interconnect layers formed above a wafer chip are quite common in semiconductor manufacturing. This is especially true in the manufacturing of logic circuit products. When components are further miniaturized and more stringent design rules are applied, new techniques for forming interconnects that go together with the planarization of dielectric layers are always in demand. At present, a contact plug is used for connecting one terminal of a MOS component with a metallic layer, and a via plug is used for interconnecting two different metallic layers. Two main plugging techniques now employed by most VLSI circuit manufacturers include the tungsten plug and the high temperature aluminum plug.
A spin on glass method is a commonly used planarization technique for planarizing inter-metal dielectric layers. One advantage of using spin on glass is its characteristic fluidity. Awkward surface structures such as trenches between one metallic line and the next that normally defy proper coverage using a conventional planarization technique can be easily filled by a spin on glass layer. Therefore, the spin on glass layer has a better step coverage capability. However, when the spin on glass layer is subsequently removed by etching, not all of the unwanted spin on glass layer can be removed. Some of the spin on glass may still remain as a residue above the metal lines, especially surrounding the metal via areas. In subsequent steps, if low pressure and high temperature processes are performed, for example, metal sputtering, plasma enhanced chemical vapor deposition (PECVD) or high temperature deposition of aluminum, residual solvent and moisture in the residual spin on glass may be driven out causing the so-called poisoned via phenomenon. These poisoned vias can lead to a number of defects. For example, the out diffusion of the solvent and moisture may lead to a volumetric expansion of the metal vias, or the solvent and moisture may react with the metal leading to a higher component resistance, or may simply cause an open circuit in the metal vias. In light of the foregoing, there is a need in the art for an improved method of planarizing the inter-metal dielectric layer using spin on glass.